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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT40103 8-bit synchronous binary down counter
Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jul 08
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
FEATURES * Cascadable * Synchronous or asynchronous preset * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the "40103" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The "40103" contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT40103
Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. The "40103" may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode.
TYPICAL SYMBOL PARAMETER tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V propagation delay CP to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 30 32 3.5 24 30 31 3.5 27 HCT ns MHz pF pF UNIT
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME 74HC40103N; 74HCT40103N 74HC40103D; 74HCT40103D 74HC40103DB; 74HCT40103DB 74HC40103PW; DIP16 SO16 SSOP16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body
74HC/HCT40103
VERSION SOT38-1 SOT109-1 SOT338-1 SOT403-1
plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION PIN NO. 1 2 3 4, 5, 6, 7, 10, 11, 12, 13 8 9 14 15 16 SYMBOL CP MR TE P0 to P7 GND PL TC PE VCC NAME AND FUNCTION clock input (LOW-to-HIGH, edge-triggered) asynchronous master reset input (active LOW) terminal enable input jam inputs ground (0 V) asynchronous preset enable input (active LOW) terminal count output (active LOW) synchronous preset enable input (active LOW) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Fig.4 Functional diagram.
FUNCTION TABLE CONTROL INPUTS PRESET MODE MR H H H H L Note 1. Clock connected to CP. Synchronous operation: changes occur on the LOW-to-HIGH CP transition. Jam inputs: MSD = P7, LSD = P0. H = HIGH voltage level L = LOW voltage level X = don't care APPLICATIONS * Divide-by-n counters * Programmable timers * Interrupt timers * Cycle/program counters PL H H H L X PE H H L X X TE H L X X X asynchronous synchronous inhibit counter count down preset on next LOW-to HIGH clock transition preset asynchronously clear to maximum count ACTION
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Fig.5 Logic diagram.
Fig.6 Timing diagram.
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 450 90 77 265 53 45 475 95 81 415 83 71 110 22 19 250 50 43 190 38 32 190 38 32 75 15 13 110 22 19
74HC/HCT40103
TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 Fig.11 Fig.10 Fig.9 Fig.9 Fig.7 Figs 7 and 8 Fig.9 Fig.9 Fig.8 Fig.7
min. typ. max. min. max. tPHL/ tPLH propagation delay CP to TC 96 35 28 tPHL/ tPLH propagation delay TE to TC 50 18 14 tPHL/ tPLH propagation delay PL to TC 102 37 30 tPHL propagation delay MR to TC 83 30 24 tTHL/ tTLH output transition time 19 7 6 tW clock pulse width HIGH or LOW 165 33 28 tW master reset pulse width LOW 125 25 21 tW preset enable pulse width PL; LOW 125 25 21 trem removal time MR to CP or PL to CP 50 10 9 tsu set-up time PE to CP 75 15 13 1998 Jul 08 22 8 6 39 14 11 33 12 10 14 5 4 22 8 6 6 300 60 51 175 35 30 315 63 53 275 55 47 75 15 13 205 41 35 155 31 26 155 31 26 65 13 11 95 19 16 375 75 64 220 44 37 395 79 40 345 69 59 95 19 16
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. 225 45 38 110 22 19 0 0 0 0 0 0 0 0 0 2.0 10 12 MHz ns ns ns ns max. ns
TEST CONDITIONS WAVEFORMS UNIT V CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 Fig.12 Fig.11 Fig.11 Fig.12 Fig.11
min. typ. max. min. max. tsu set-up time TE to CP 150 30 26 tsu set-up time Pn to CP hold time PE to CP 75 15 13 th 0 0 0 th hold time TE to CP 0 0 0 th hold time Pn to CP maximum clock pulse frequency 0 0 0 fmax 3.0 15 18 44 16 13 22 8 6 -14 -5 -4 -30 -11 -9 -17 -6 -5 10 29 35 190 38 33 95 19 16 0 0 0 0 0 0 0 0 0 2.4 12 14
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI
74HC/HCT40103
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT CP, PE MR TE PL Pn UNIT LOAD COEFFICIENT 1.50 1.00 0.80 0.35 0.25
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. 90 60 112 83 22 50 45 57 15 30 60 ns ns ns ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.8 Fig.9 Fig.9 Figs. 7 and 8 Fig.7 Fig.9 Fig.9 Fig.10 Fig.11 Fig.11 UNIT V WAVEFORMS CC (V) TEST CONDITIONS
min. typ. max. min. max. min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH tW tW tW trem tsu tsu propagation delay CP to TC propagation delay TE to TC propagation delay PL to TC propagation delay MR to TC output transition time clock pulse width HIGH or LOW master reset pulse width LOW preset enable pulse width PL; LOW removal time MR to CP or PL to CP set-up time PE to CP set-up time TE to CP 33 30 38 10 20 40 35 23 44 29 7 10 16 22 1 11 20 60 40 75 55 15 41 38 48 13 25 50 75 50 94 69 19
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. ns ns ns ns MHz
TEST CONDITIONS WAVEFORMS UNIT V CC (V) 4.5 4.5 4.5 4.5 4.5 Fig.12 Fig.11 Fig.11 Fig.12 Fig.7
min. typ. max. min. max. min. tsu th th th fmax set-up time Pn to CP hold time PE to CP hold time TE to CP hold time Pn to CP maximum clock pulse frequency 20 2 0 0 15 11 -3 -10 -5 28 25 2 0 0 12 30 2 0 0 10
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
AC WAVEFORMS
74HC/HCT40103
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the clock input (CP) to TC propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency.
Fig.8
Waveforms showing the TE to TC propagation delays.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9
Waveforms showing PL, MR, Pn to TC propagation delays.
Fig.10 Waveforms showing removal time for MR and PL.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing hold and set-up times for MR or PE to CP.
Fig.12 Waveforms showing hold and set-up times for Pn, PE to CP.
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
APPLICATION INFORMATION
74HC/HCT40103
Fig.13 Programmable timer.
VCC f IN N1
P0
TC TE PE
f OUT =
N
40103 PL MR P7 GND
MGA836
CP
f IN
Fig.14 Divide-by-N counter.
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
74HC/HCT40103
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-02 95-01-19
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1998 Jul 08
13
Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 pin 1 index Lp L 1 bp 8 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-01-14 95-02-04
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
74HC/HCT40103
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
74HC/HCT40103
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: * Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). * Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
1998 Jul 08
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Philips Semiconductors
Product specification
8-bit synchronous binary down counter
REPAIRING SOLDERED JOINTS
74HC/HCT40103
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1998 Jul 08
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